A delay element is used in many electronic circuits to delay one or more signals. In a typical implementation one or more delay elements are arranged serially in what is referred to as a delay line to serially delay a signal. A typical clock signal is provided as a signal that varies over a 360 degree phase. Typical delay lines can delay the output phase of a clock signal by any amount within the 360 degree phase over a band of different frequencies. One typical implementation of a delay line, or a delay lock loop, for use in a phase detector employs an exclusive OR (XOR) logic element. Unfortunately, when implementing a delay locked loop phase detector using an XOR element, allowing the output phase of a clock signal to be delayed more than 180 degrees allows such a phase detector to lock into multiple and possibly non-optimal modes. Implementing a single delay element may be able to compensate for this deficiency. However, a conventional delay element can only delay an input clock signal from the minimum intrinsic gate delay value to a maximum delay of 90 degrees. Further, a conventional delay element attenuates the input signal as the delay is increased and typically requires that the output signal be amplified to a useful level. This attenuation effect limits the lower bandwidth of the circuit.
Therefore, it would be desirable to have a variable delay element that overcomes these shortcomings.